--
-- VHDL Package Header ARMa_lib.ARMa_types
--
-- Created:
--          by - Administrator.UNKNOWN (ECE-5BF87F3CFF5)
--          at - 04:18:18 9/25/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

PACKAGE ARMa_types IS
-- Signal widths
  SUBTYPE ARMa_byte IS std_logic_vector(7 downto 0);
  SUBTYPE ARMa_word IS std_logic_vector(31 downto 0);
  SUBTYPE ARMa_reg IS std_logic_vector(3 downto 0);
  SUBTYPE ARMa_imm8 is std_logic_vector(7 downto 0);
  SUBTYPE ARMa_opcode IS std_logic_vector(7 downto 0);

-- Time delays (added for ease of use)
  constant delay_ALU : time := 15 ns;
  constant delay_ALU_ctrl : time := 5 ns;
  constant delay_adder : time := 5 ns;
  constant delay_regfile_read : time := 8 ns;
  constant delay_reg : time := 4 ns;
  constant delay_MUX2 : time := 2 ns;
  constant delay_MEM : time := 50 ns;

END ARMa_types;